Myricom 10G-PCIE-8B-2S NIC Specifications

Product photo Product Codes:
• 10G-PCIE-8B-2S: NIC with a standard PCI faceplate
• 10G-PCIE-8BL-2S: NIC with a low-profile PCI faceplate

Key Features:
• Low-profile PCI Express x8 add-in card
• Dual-protocol network ports, 10-Gigabit Ethernet or 10-Gigabit Myrinet
• Wire-speed performance from either port
• Firmware-controlled offloads
• 6 Watts typical including power for two SFP+ transceivers

Note: This two-port NIC appears to the host operating system as a single PCI Express device. Firmware provides failover between the two network ports with a response time that can be set to as little as ~10µs. Concurrent wire-speed operation from two 10Gb ports requires higher data rates to/from the host than a "Gen 1" (2.5 GT/s) PCI Express x8 slot can provide. If your application requires two ports for performance and failover, see the 10G-PCIE2-8B2-2S NIC, which has a "Gen 2" (5 GT/s) PCI Express x8 host port.

Specifications:

Myri-10G network ports (2): SFP+ (Small Form factor Pluggable) sockets for SFP+ transceivers, either 10GBase-SR or 10GBase-LR, 10+10 Gbit/s data rate, full-duplex. The SFP+ sockets provide SFI 10.3125 GBaud 64b/66b-encoded signaling, electrical power, and the standard SFP+ management interface. The sockets do not require the use of SFP+ transceivers purchased from Myricom. The sockets may also be used with SFP+-terminated twinax "Direct Attach" copper cables up to 5m, or with SFP+-terminated EOE cables. The ports can operate with either Ethernet or Myrinet protocols at the Data Link layer. When operating in Ethernet mode, the port supports Ethernet flow control as defined by IEEE 802.3x. The allowed length of the fiber cable depends upon the SFP+ transceiver and the quality of the fiber, but in Myrinet mode must not exceed 200m due to Myrinet flow control. (See this Guide to Myri-10G PHYs (pdf).)

Laser Safety: When used with 10GBase-SR or 10GBase-LR SFP+ transceivers, this NIC is a Class 1 Laser Product (no biological hazard).

PCI Express host port: This NIC is an x8 (8 lane) PCI Express Add-in Card. It is capable of exchanging data with a host computer at up to 2 GBytes/s (250 MBytes/s per lane) data rate in each direction, full-duplex. This NIC is fully compliant with the PCI Express Card Electromechanical Specification Rev. 2.0, and with the PCI Express Base Specification Rev. 2.0 (2.5 GT/s only). The circuit-board edge connector of the NIC will fit mechanically in x8 or x16 physical slots in host computers. The NIC auto-negotiates operation in the widest available mode (x8, x4, x2, or x1) supported by the slot it is plugged into.

Optional PCI Express capabilities supported: Advanced Error Reporting, Function-Level Reset, Device Serial Number, up to 16 outstanding read requests, up to 4KB MaxPayloadSize for all packet types, MSI and MSI/X, SMBus access.

Optional PCI Express capabilities to be supported in upcoming firmware releases: Address Translation Services, Single Root I/O Virtualization and Sharing, Alternative Routing-ID Interpretation.

These NICs have been tested and qualified in many commercially available motherboards and with all of the common PCI Express chip sets. See this tabulation for the test results with different "Gen1" (2.5 GT/s) PCI Express chip sets. These NICs have also been tested in "Gen2" PCI Express slots, in which the NIC auto-negotiates operation at "Gen1" PCI Express data rates.

NIC processor and memory: The NIC is based on a Myricom custom-VLSI chip, the Lanai Z8ES, which includes a programmable RISC, a set of packet engines, and 2MB of fast SRAM. The RISC, packet engines, and SRAM inside the Lanai-Z8ES chip operate at a clock rate of 364.6MHz. Byte parity is generated and checked on all on-chip memories.

EEPROM: 1MB, which includes the firmware required for PCI device initialization and an Etherboot (UEFI- and PXE-compatible) driver. The driver loads the matching firmware as required by the mode in which the NIC is operating. The EEPROM can be re-programmed in-place by the Lanai Z8ES.

LEDs (3): The yellow LED on the PCI faceplate is controlled by the Lanai firmware; its interpretation is different for different firmware. There is also a green LED for each port: off indicates that the link is down, on indicates that the link is up, and blinking indicates traffic.

Physical characteristics: The circuit board is a low-profile add-in card as defined in the PCI Express Card Electromechanical Specification Rev. 2.0: height 68.9mm (exclusive of the PCI faceplate), length 124.5mm (exclusive of the PCI faceplate), total thickness 22mm, weight 60g (0.13 pound) including the standard PCI faceplate. The NIC can be supplied with either a standard PCI faceplate (10G-PCIE-8B-2S) or a low-profile PCI faceplate (10G-PCIE-8BL-2S).

Power: The NIC is powered from 3.3V from the PCI Express port, 2.0A (6.6W) maximum, 1.8A (6W) typical, including 1W for each of two SFP+ transceivers. When used with "Direct Attach" twinax copper cables, the typical power is 4W.

Environmental: Operating: Temperature 0C to 55C up to 10,000 foot altitude with 100LFM minimum airflow. Relative humidity 15% to 80% @ 50C, non-condensing. Storage: Temperature -40C to 70C. Relative humidity 90% @ 65C.

Regulatory Approvals: Fully compliant with EN55024 (1998 w/A1: 2001 & A2: 2003), EN55022 (1998) Class A, AS/NZS 3548 (1005 W/A1 & A2: 97) Class A, CISPR 22 (1997) Class A, FCC Part 15 Subpart B Section 15.109 Class A, VCCI (April 2000) Class A, & ICES-003 Class A (ANSI C63.4 1992). See the Index of Myri-10G Regulatory Reports.

Reduction of Hazardous Substances: These NICs are RoHS-compliant under the server exemption.

Myricom-supported software: These NICs may use the included (bundled) Myri10GE software for 10-Gigabit Ethernet operation, or optional software distributions including MX-10G, Video Pump, Sniffer10G, or DBL. This software is distributed from the Myricom Software & Customer Support page.