M3F-PCI64B & M3F-PCI64C Universal, 64/32-bit, 66/33MHz, Myrinet-2000-Fiber/PCI interfaces |
These universal, 64/32-bit, 66/33MHz, Myrinet-2000-Fiber/PCI interfaces are ideal for the most demanding cluster and distributed-computing applications. The interface includes a fast RISC to execute the Myrinet control program, a versatile DMA controller to support zero-copy APIs, and a complete set of high-availability and data-integrity features. The difference between the PCI64B and PCI64C interfaces is the allowed clock rate of the RISC and local memory: 133MHz for the PCI64B, and 200MHz for the PCI64C.
Block diagram
PCI-bus Interface: 64/32-bit, 66/33MHz, supports all burst modes and write-invalidate, master or slave. These interfaces are capable of sustained PCI data rates approaching the limits of the PCI bus (528 MB/s for 64-bit, 66MHz; 264 MB/s for 64-bit, 33MHz or 32-bit, 66MHz; 132 MB/s for 32-bit, 33MHz). However, the data rate to/from system memory will depend upon the host's memory and PCI-bus implementation. These interfaces function correctly in all PCI slots that are compliant with PCI specifications (version 2.2), with either 3.3V or 5V PCI-bus signal levels. (3.3V signaling is required of 66MHz PCI slots, but 33MHz PCI slots may use either 5V or 3.3V signaling.) PCI parity generation and detection is provided. The interface provides a 64-bit Base Address Register (BAR), but will also function properly when programmed with a 32-bit address, per the PCI specifications.
DMA controller: Traverses multiple lists in the interface's local memory to initiate DMA transfers, thus allowing multiple pending DMA operations. In order to support zero-copy APIs efficiently, the DMA operations can be performed with arbitrary byte counts and byte alignments. The DMA controller computes the IP checksum for each transfer. The DMA controller also provides a "doorbell" signalling mechanism that allows the host to write anywhere within the doorbell region, and have the address and data stored in a FIFO queue in the local memory.
Interface processor: LANai 9 RISC operating at up to 133MHz for the PCI64B interfaces, or at up to 200MHz for the PCI64C interfaces. Note: the RISC in the LANai 9 is similar to but is not binary-compatible with earlier LANai RISCs.
Local memory: 2MB (256Kx8B) in the -2 version; 4MB (512Kx8B) in the -4 version, 8MB (1Mx8B) in the -8 version. The local memory operates from the same clock as the RISC, i.e., at up to 133 MHz for the PCI64B interfaces, or at up to 200MHz for the PCI64C interfaces. Up to 1,067 MB/s (PCI64B) or 1,600 MB/s (PCI64C) of memory bandwidth is available to support the Myrinet port, the host DMA, and the RISC processor. Byte parity is generated and checked.
Myrinet-2000-Fiber port: 2.0+2.0 Gb/s. An "LC" optical connector attaches to a fiber pair up to 200m of 50/125 multi-mode fiber. This is a Class I Laser Product (no biological hazard).
Physical dimensions: PCI Short Card: height 10.7cm, length 18.0cm, total thickness 2.5cm, weight 120g.
Power: The interface is powered from the 5V PCI power: 1.9A (9.5W) maximum for the M3F-PCI64B-2; 2.2A (11.0W) maximum for the M3F-PCI64C-2.
Regulatory Approvals: Fully compliant with EN55024 (1998), EN55022 Class A (1995), VCCI Class A (May 1999), FCC Part 15 Subpart B Class A, CISPR 22/85 Class A, ICES-003 Class A (ANSI C63.4 1992), and AS/NZS 3548 Class A (w/A1 & A2 1997). CE Declaration of Conformity. M3F-PCI64C-2 EMC Test Report.
Myricom-supported software: Open source, distributed from the Myrinet Software & Customer Support page. These interfaces require the use of the GM software; the MyriAPI software is not available for the PCI64 family of interfaces.
Programmer's Documentation for customers who write their own Myrinet control programs.
Note: The implementation of this family of interfaces went through a "mid-life improvement" in December 2001. The interface pictured below is of the new type, which is form, fit, and function equivalent to its predecessor, and hence has the same product code. In this new version, the Serializer-Deserializer (SerDes) chip that drives the optical-fiber transceiver was changed to a CMOS part, which dissipates ~1.25W less power and has a higher operating-temperature range than the previous GaAs part. The easiest way to distinguish the two versions is that the earlier version had a large, black, heat sink on the SerDes chip, which is between the Myricom SerDes-SAN chip and the optical-fiber transceiver.
M3F-PCI64C-2 Myrinet-2000-Fiber/PCI Interface
Last updated: 25 July 2002